1. Field of the Invention
The present invention relates to an operational amplifier, a drive circuit using the operational amplifier, and a method for driving a liquid crystal display device using the operational amplifier. More particularly, the present invention relates to an operational amplifier used to drive a capacitive load, such as a liquid crystal panel, a drive circuit using the operational amplifier, and a method for driving a liquid crystal display device using the operational amplifier.
2. Description of the Related Art
Conventionally, an operational amplifier has been configured using bipolar transistors in most cases. For reasons of a growing need for the coexistence of bipolar transistors with a MOS circuit and for low-power operation, however, the operational amplifier is configured using MOS transistors more often than ever these days. When configuring the operational amplifier with MOS transistors, there is the case that a circuit configuration different from that of an operational amplifier configured with bipolar transistors is adopted by taking advantage of analog characteristics inherent in a MOS transistor. Examples of such an operational amplifier include an amplifier using an electronic switch function.
One of the application areas of an operational amplifier configured with MOS transistors is a TFT LCD (Thin Film Transistor Liquid Crystal Display) driver LSI (see, for example, Japanese Patent Laid-Open No. 61-35004). This LCD driver LSI includes a plurality of operational amplifiers having a voltage follower configuration as output buffer amplifiers and gray-scale power supplies for gamma-correction. The LCD driver LSI is required to have only a small difference in offset voltage among this plurality of operational amplifiers. This is because even a voltage difference of 10 mV is recognized as a distinct gray-scale level for human eyes for reasons of the characteristics of a TFT LCD. Hence, there is a demand in this area for a MOS operational amplifier having an extremely small offset voltage.
FIGS. 7 and 8 are circuit diagrams showing configuration examples of an operational amplifier used to drive a conventional liquid crystal display device described in Japanese Patent Laid-Open No. 11-249623. Referring to FIG. 7, the conventional operational amplifier includes PMOS transistors MP1 and MP2, a constant current source I1, NMOS transistors MN1, MN2 and MN3, a constant current source I2, a phase-compensating capacitor C, and switches S1, S2, S3, S4, S5, S6, S7 and S8.
The two PMOS transistors MP1 and MP2 constitute a differential pair. The constant current source I1 biases this differential pair and is inserted between a point to which the sources of the PMOS transistor MP1 and MP2 are connected in common and a positive power supply VDD. The NMOS transistors MN1 and MN2 are configured as a current mirror and serve also as an active load and a differential-to-single-ended conversion function. The NMOS transistor MN3 constitutes a second-stage amplifier circuit. The constant current source I2 is inserted between the drain of the NMOS transistor MN3 and the positive power supply VDD. This constant current source I2 serves as the active load of the NMOS transistor MN3. The phase-compensating capacitor C is inserted between the gate and the drain of the NMOS transistor MN3.
Here, the technical terms to be referred to hereinafter will be described. A “make-type switch” refers to a type of switch which closes when a control signal is input. In contrast, a “break-type switch” refers to a type of switch which opens when a control signal is input. In addition, a “transfer-type switch” refers to a type of switch which has a common terminal and two output terminals (make-side and break-side terminals) in which the common terminal and the make-side terminal go into a connected state when a control signal is input, and the common terminal and the break-side terminal go into a connected state when a control signal is not input.
A break-type switch S1 is inserted between the gate and the drain of the NMOS transistor MN1. In addition, a make-type switch S2 is inserted between the gate and the drain of the NMOS transistor MN2. A make-type switch S3 is connected between the drain of the NMOS transistor MN1 and the gate of the NMOS transistor MN3. A break-type switch S4 is connected between the drain of the NMOS transistor MN2 and the gate of the NMOS transistor MN3. A make-type switch S5 is connected between the gate of the PMOS transistor MP2 and an output terminal Vout. A break-type switch S6 is connected between the gate of the PMOS transistor MP1 and the output terminal Vout. A make-type switch S7 is connected between the gate of the PMOS transistor MP1 and an input terminal Vin. A break-type switch S8 is connected between the gate of the PMOS transistor MP2 and the input terminal Vin.
The drain of one PMOS transistor MP1 constituting the differential pair is connected to the drain of the NMOS transistor MN1. In addition, the drain of the other PMOS transistor MP2 constituting the differential pair is connected to the drain of the NMOS transistor MN2. The switches S1 to S8 are all controlled in conjunction with one another. The amplifier shown in FIG. 7 is used to output a supply voltage from VSS to VCOM (VDD/2) (so-called negative output) and has the characteristic that the switches S1 to S8 are operated for each frame or each single horizontal scan period. Note that FIGS. 7A and 7B show two states (states A and B) which these switches S1 to S8 take when operated.
Referring to FIG. 7, the conventional operational amplifier includes NMOS transistors MN1 and MN2, a constant current source I1, PMOS transistors MP1, MP2 and MP3, a constant current source I2, a phase-compensating capacitor C, and switches S1, S2, S3, S4, S5, S6, S7 and S8.
The two NMOS transistors MN1 and MN2 constitute a differential pair. The constant current source I1 biases this differential pair and is inserted between a point to which the sources of the NMOS transistor MN1 and MN2 are connected in common and a negative power supply VSS. The PMOS transistors MP1 and MP2 are configured as a current mirror and serve also as an active load and a differential-to-single-ended conversion function. The PMOS transistor MP3 constitutes a second-stage amplifier circuit. The constant current source I2 is inserted between the drain of the PMOS transistor MP3 and the negative power supply VSS. This constant current source I2 serves as the active load of the PMOS transistor MP3. The phase-compensating capacitor C is inserted between the gate and the drain of the PMOS transistor MP3.
A break-type switch S1 is inserted between the gate and the drain of the PMOS transistor MP1. In addition, a make-type switch S2 is inserted between the gate and the drain of the PMOS transistor MP2. A make-type switch S3 is connected between the drain of the PMOS transistor MP1 and the gate of the PMOS transistor MP3. A break-type switch S4 is connected between the drain of the PMOS transistor MP2 and the gate of the PMOS transistor MP3. A break-type switch S5 is connected between the gate of the NMOS transistor MN2 and an output terminal Vout. A break-type switch S6 is connected between the gate of the NMOS transistor MN1 and the output terminal Vout. A break-type switch S7 is connected between the gate of the NMOS transistor MN1 and an input terminal Vin. A make-type switch S8 is connected between the gate of the NMOS transistor MN2 and the input terminal Vin.
The drain of one NMOS transistor MN1 constituting the differential pair is connected to the drain of the PMOS transistor MP1. In addition, the drain of the other NMOS transistor MN2 constituting the differential pair is connected to the drain of the PMOS transistor MP2. The switches S1 to S8 are all controlled in conjunction with one another. The amplifier shown in FIG. 8 is used to output a supply voltage from VCOM (VDD/2) to VDD (so-called positive output) and has the characteristic that the switches S1 to S8 are operated for each frame or each single horizontal scan period. Note that FIGS. 8A and 8B show two states (states A and B) which these switches S1 to S8 take when operated.
Next, FIG. 9 shows examples of application in which the amplifiers shown in FIGS. 7 and 8 are applied to an LCD driver. In the LCD driver shown in FIG. 9, the amplifier shown in FIG. 8 is applied to an AMP1 and the amplifier shown in FIG. 7 is applied to an AMP2.
Transfer-type switches (SW1 and SW2) are respectively provided in the outputs of the AMP1 and AMP2. The switches SW1 and SW2 select between the outputs of the AMP1 and AMP2 for an odd-numbered output terminal (Vout odd) and an even-numbered output terminal (Vout even). At this time, if one state is taken for example, then the output of the AMP1 is output to the odd-numbered output terminal and the output of the AMP2 is output to the even-numbered output terminal. Alternatively, the other state reverses the above-described operation. That is, the output of the AMP1 is output to the even-numbered output terminal and the output of the AMP2 is output to the odd-numbered output terminal.
Positive-side data is input to an input of the AMP1 and negative-side data is input to an input of the AMP2. By connecting the amplifiers in this way and driving the switches SW1 and SW2 in an interlocked manner on a frame-by-frame basis, such an output image as shown in FIG. 10 is obtained. Note that in a driving method known as dot-inversion driving, these switches SW1 and SW2 are operated for each single horizontal scan period. This method will not be described in detail here, however.
The conventional operational amplifier circuit shown in FIG. 7 is configured with the PMOS transistors MP1 and MP2 constituting a differential pair and the NMOS transistors MN1 and MN2 configured as a current mirror and serving also as the active load and the differential-to-single-ended conversion function of the differential pair. Here, when the switch S1 closes, the drain of the N-channel MOS transistor MN2 serves as the single-ended output thereof. When the switch S2 closes, the drain of the N-channel MOS transistor MN1 serves as the single-ended output thereof. The output terminal changes in this way according to the states of the switches S1 and S2 and, therefore, the switches S3 and S4 are provided for output selection. A signal subjected to single-ended conversion through these switches S3 and S4 is input to the gate of the NMOS transistor MN3 which is an output transistor. At this time, the constant current source I2 functions as the active load of the NMOS transistor MN3. In addition, the drain of the NMOS transistor MN3 serves as the output terminal. The capacitor C provided as a mirror capacitor functions as a phase compensator.
In order to use the operational amplifier circuit as a buffer amplifier, the circuit is configured to form a so-called voltage follower connection in which the inverting input terminal and the output terminal are connected to each other. The voltage follower connection is a connection method in which the inverting input terminal and the output terminal of an amplifier are connected to each other and an input signal is applied to the non-inverting input terminal so that the signal is output from the output terminal of the amplifier. This method causes the same voltage as the input voltage to be output. When the switches S1 to S4 are operated, the inverting input terminal changes to the gate of the PMOS transistor MP1 or to the gate of the PMOS transistor MP2. Accordingly, the switches S5 and S6 are provided to select the inverting input terminal between these gates. That is, when the switches S1 and S4 close, the inverting input terminal changes to the gate terminal of the PMOS transistor MP1. Accordingly, by closing the switch S6 at this time, the inverting input terminal and the output terminal are connected in common to each other to form a voltage follower connection. Since the non-inverting input terminal changes to the gate terminal of the PMOS transistor MP2, the switch S8 is closed to connect the gate terminal to the input terminal Vin.
Conversely, when the switches S2 and S3 close, the inverting input terminal changes to the gate terminal of the PMOS transistor MP2. Consequently, the inverting input terminal and the output terminal are connected in common to each other by closing the switch S5 at this time, thereby forming a voltage follower connection. Since the non-inverting input terminal changes to the gate terminal of the PMOS transistor MP1, the switch S7 is closed to connect the gate terminal to the input terminal Vin. This means that operating the switches S1 to S8 gives rise to two states (states A and B). These two states are switched between on a frame-by-frame basis (or for each single horizontal scan period).
Now, assume that an offset voltage +Vos has been produced in the conventional operational amplifier of FIG. 7. Then, the offset voltage changes to −Vos when the switches S1 to S8 are operated. Consequently, operating these switches S1 to S8 for each two frames (or for each single horizontal scan period) causes the offset voltage to disperse spatially. Thus, on average, the offset voltage equals zero. Accordingly, the offset voltage is recognized as the averaged voltage, i.e., as being zero, for human eyes. In other words, this method is intended to play tricks on human eyes.
Since the amplifier of FIG. 7 is a differential stage configured with PMOS transistors, it is not possible to apply a voltage as high as or higher than VDD−1 V to the input on the positive power supply I1 side. This is because the bias current source I1 no longer operates due to the gate-source voltages of the PMOS transistors MP1 and MP2 in the differential stage. However, for voltages near the VSS, it is possible to input a voltage of almost up to the VSS, though this depends on the gate-source voltages of the NMOS transistors MN1 and MN2 serving as an active load.
The conventional operational amplifier circuit of FIG. 8 is configured with the NMOS transistors MN1 and MN2 constituting a differential pair and the PMOS transistors MP1 and MP2 configured as a current mirror and serving as the active load and the differential-to-single-ended conversion function of the differential pair. Here, when the switch S1 closes, the drain of the PMOS transistor MP2 serves as the single-end output thereof and, when the switch S2 closes, the drain of the PMOS transistor MP1 serves as the single-ended output thereof. The output terminal changes in this way according to the states of the switches S1 and S2 and, therefore, the switches S3 and S4 are provided for output selection. A signal subjected to single-ended conversion through these switches S3 and S4 is input to the gate of the PMOS transistor MP3 which is an output transistor. At this time, the constant current source I2 functions as the active load of the PMOS transistor MP3. In addition, the drain of the PMOS transistor MP3 serves as the output terminal. The capacitor C provided as a mirror capacitor functions as a phase compensator. In order to use the operational amplifier circuit as a buffer amplifier, the circuit is configured to form a so-called voltage follower connection in which the inverting input terminal and the output terminal are connected to each other.
When the switches S1 to S4 are operated at this time, the inverting input terminal changes to the gate of the NMOS transistor MN1 or to the gate of the NMOS transistor MN2. Accordingly, the switches S5 and S6 are provided to select the inverting input terminal between these gates. That is, when the switches S1 and S4 close, the inverting input terminal changes to the gate terminal of the NMOS transistor MN1. Accordingly, the switch S6 is closed at this time to connect the inverting input terminal and the output terminal to each other to form a voltage follower connection. Since the non-inverting input terminal changes to the gate terminal of the NMOS transistor MN2, the switch S8 is closed so that the gate terminal of the NMOS transistor MN2 is connected to the input terminal Vin.
Conversely, when the switches S2 and S3 close, the inverting input terminal changes to the gate terminal of the NMOS transistor MN2. Consequently, the inverting input terminal and the output terminal are connected in common to each other by closing the switch S5 at this time, thereby forming a voltage follower connection. Since the non-inverting input terminal changes to the gate terminal of the NMOS transistor MN1, the switch S7 is closed so that the gate terminal of the NMOS transistor MN1 is connected to the input terminal Vin. This means that operating the switches S1 to S8 gives rise to two states (states A and B). These two states are switched between on a frame-by-frame basis (or for each single horizontal scan period). Now, assume that an offset voltage +Vos has been produced in the conventional operational amplifier of FIG. 8. Then, the offset voltage changes to −Vos when the switches S1 to S8 are operated. Consequently, operating these switches S1 to S8 on a frame-by-frame basis (or for each single horizontal scan period) causes the offset voltage to disperse spatially, as in the case of FIG. 7. Thus, on average, the offset voltage equals zero. Accordingly, the offset voltage is recognized as the averaged voltage, i.e., as being zero, for human eyes.
Since the amplifier of FIG. 8 is a differential stage configured with NMOS transistors, it is not possible to apply a voltage as low as or lower than VSS+1 V to the input on the negative power supply side. This is because the bias current source I1 no longer operates due to the gate-source voltages of the NMOS transistors MN1 and MN2 in the differential stage. However, for voltages near the VDD, it is possible to input a voltage of almost up to the VDD, though this depends on the gate-source voltages of the PMOS transistors MP1 and MP2 serving as an active load.
FIG. 9 is a circuit diagram showing a configuration of an LCD driver which uses the amplifiers of FIGS. 7 and 8. Referring to FIG. 9, the amplifier for positive-side use only shown in FIG. 8 is used for a positive-side (VDD/2 to VDD) amplifier AMP1 and the amplifier for negative-side use only shown in FIG. 7 is used for a negative-side (VSS to VDD/2) amplifier AMP2. The respective outputs of these amplifiers are provided with selector switches so that a signal can be output either to an odd-numbered output (Vout_odd) or to an even-numbered output (Vout_even). Consequently, it is possible to output either a positive-side voltage or a negative-side voltage to the output in question no matter whether the output is an odd-numbered output or an even-numbered output. This is a conventional, so-called two-amplifier system.
Now, an explanation will be made of a method for driving an LCD driver called dot-inversion driving. Dot-inversion driving is a driving method in which a positive (+) polarity signal and a negative (−) polarity signal are alternately output on a dot-by-dot basis on the basis of a VCOM. In addition, the polarity of a signal to be output to each dot needs to be inverted on a frame-by-frame basis. Accordingly, the driving method needs to be implemented with each four frames grouped into one set, as shown in FIG. 10, in order to perform offset canceling using a frame signal. This means that if a positive (+) polarity signal is output by the AMP1 in a first frame, then a negative (−) polarity signal is output by the AMP2 in a second frame. At this time, an offset-canceling signal is not changed in the first and second frames. Then, in a third frame, the offset-canceling signal is inverted to output a positive (+) polarity signal by the AMP1. In a fourth frame, a negative (−) polarity signal is output by the AMP2 with the offset-canceling signal also inverted.
Note here that it is a sum of the absolute values of positive (+) and negative (−) side amplitudes that affects image quality. In FIG. 10, if a difference between an amplitude denoted as “amplitude A” and an amplitude denoted as “amplitude B” remains the same, then the two amplitudes are recognized as being of the same gray scale. Accordingly, if the absolute value of an offset voltage based on an offset-canceling control signal is the same on each of the positive and negative sides before and after control, then the amplitude A and the amplitude B result in the same value. Offset canceling can be realized in this way. The difference between the amplitudes A and B is referred to as an “amplitude difference deviation” and is the most important parameter in an LCD driver. This amplitude difference deviation, if too large, may cause such a problem that vertical streaks appear on an LCD display.
However, if the LCD driver is configured as shown in FIG. 9 by exclusively using the amplifier shown in FIG. 7 on the negative side and the amplifier shown in FIG. 8 on the positive side, the LCD driver cannot meet the requirements for a driving method called 2H inversion driving. This 2H inversion driving is a method for driving the positive-side or negative-side voltage for two horizontal scan periods in a row. FIG. 11 shows an output signal of the 2H inversion driving method. The current-sourcing capacity of the amplifier shown in FIG. 7 is only as large as that of the current source I2 at the maximum and the current-sinking capacity of the amplifier shown in FIG. 8 is only as large as that of the current source I2 at the maximum. Thus, the amplifiers have no larger drive current capacities than those described above. Accordingly, in the 1Hth rising waveform shown in FIG. 11, for example, the operation of the amplifier of FIG. 8 is current-sourcing operation and, therefore, there is no problem. However, if the voltage of the 2Hth waveform is lower than that of the 1Hth waveform, the amplifier is current-sinking operation, thus falling short of drive current. Note that it is possible to allow the amplifier shown in FIG. 7 to have a significantly large current-sinking capacity, though this depends on the size of the NMOS transistor MN3. Likewise, it is possible to allow the amplifier shown in FIG. 8 to have a significantly large current-sourcing capacity, though this depends on the size of the PMOS transistor MP3.
Furthermore, the amplifiers shown in FIGS. 7 and 8, when used for the gamma amplifiers (which refer to amplifiers for adjusting the gamma characteristic of the LCD panel by applying voltages to the respective taps of a gamma resistor, though not shown in the figure) of an LCD panel, only have the capability of driving one polarity and is, therefore, not adoptable.